Re: [PATCH 0/3] NUMA boot hash allocation interleaving

[Andi Kleen <ak@suse.de>]

On Wed, Dec 15, 2004 at 08:41:25AM +0100, Eric Dumazet wrote:
> 
> My questions are :
> 
> 1) Are the route cache and tcp hashes use big pages (2MB) on 2.6.5/2.6.9 
> x86_64 kernels.

Yes.

On i386 kernels you can use mem=nopentium to force 4K pages for
the direct mapping, but that was dropped on x86-64. 

> 2) What are the exact number of data TLB entries (for small pages and 
> huge ones) for opterons ?

check the data sheets, but iirc 64 large DTLBs and 1024+ 4K DTLBS.
That is the L2 TLB, there is also a L1 but it is likely inclusive (?)

> 3) All networks interrupts are handled by CPU0. Should we really use 
> NUMA interleaved memory for hashes in this case ?

First it depends on if you run irqbalanced or not and how many
interrupt sources you have.

Even when they are only handled on irq0 it can be still a good idea
to interleave to use the bandwidth of all memory controllers
in the system evenly.

-Andi
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