From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
To: Arjan van de Ven <arjanv@redhat.com>
Cc: akpm@osdl.org, "Martin J. Bligh" <mbligh@aracnet.com>,
linux-mm@kvack.org
Subject: Re: [PATCH] shrink per_cpu_pages to fit 32byte cacheline
Date: Tue, 14 Sep 2004 19:45:55 -0300 [thread overview]
Message-ID: <20040914224555.GA714@logos.cnet> (raw)
In-Reply-To: <20040914114412.GC21362@devserv.devel.redhat.com>
On Tue, Sep 14, 2004 at 01:44:12PM +0200, Arjan van de Ven wrote:
> On Tue, Sep 14, 2004 at 07:01:52AM -0300, Marcelo Tosatti wrote:
> > On Tue, Sep 14, 2004 at 01:13:29PM +0200, Arjan van de Ven wrote:
> > > On Tue, Sep 14, 2004 at 06:34:07AM -0300, Marcelo Tosatti wrote:
> > > > How come short access can cost 1 extra cycle? Because you need two "read bytes" ?
> > >
> > > on an x86, a word (2byte) access will cause a prefix byte to the
> > > instruction, that particular prefix byte will take an extra cycle during execution
> > > of the instruction and potentially reduces the parallal decodability of
> > > instructions....
> >
> > OK thanks Arjan, where did you read this? The "Intel IA32 Optimization Guide" ?
>
> some version of that; I can't find it in my current one though. Hrmpf
> Maybe there's someone from intel or amd on this list who can confirm the
> performance impact of the 0x66 operand size override prefix
Prefix "data16" I see... Well it doesnt seem anyone really familiar with this
is part of the list - who you think would be sure about this?
Jun Nakajima maybe?
We need to be sure because we've just done for pagevec's.
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next prev parent reply other threads:[~2004-09-14 22:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-09-13 23:38 Marcelo Tosatti
2004-09-14 6:10 ` Arjan van de Ven
2004-09-14 9:34 ` Marcelo Tosatti
2004-09-14 11:13 ` Arjan van de Ven
2004-09-14 10:01 ` Marcelo Tosatti
2004-09-14 11:44 ` Arjan van de Ven
2004-09-14 22:45 ` Marcelo Tosatti [this message]
2004-09-15 0:57 ` Nick Piggin
2004-09-15 0:48 ` Marcelo Tosatti
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