From: Cort Dougan <cort@fsmlabs.com>
To: "David S. Miller" <davem@redhat.com>
Cc: blah@kvack.org, torvalds@transmeta.com, tytso@mit.edu,
linux-kernel@vger.kernel.org, linux-mm@kvack.org
Subject: Re: [RFC] atomic pte updates for x86 smp
Date: Wed, 11 Oct 2000 22:31:38 -0600 [thread overview]
Message-ID: <20001011223138.B962@hq.fsmlabs.com> (raw)
In-Reply-To: <200010120406.VAA07624@pizda.ninka.net>; from David S. Miller on Wed, Oct 11, 2000 at 09:06:45PM -0700
} Date: Thu, 12 Oct 2000 00:03:31 -0400 (EDT)
} From: "Benjamin C.R. LaHaise" <blah@kvack.org>
}
} It's safe because of how x86s hardware works
}
} What about other platforms?
On the PPC's that don't do a hardware walk we do a normal write to the
hash table (with a spinlock). On the hardware walk PPC's I'm told this is
done with with a lwarx/stwcx pair (conditional load/store on exclusive
access).
Any comments on how this would affect PPC?
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next prev parent reply other threads:[~2000-10-12 4:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200010090419.e994JQT09775@trampoline.thunk.org>
2000-10-10 20:53 ` Updated 2.4 TODO List Rik van Riel
2000-10-11 0:06 ` 2.4.0test9 vm: disappointing streaming i/o under load Chris Evans
2000-10-11 11:38 ` Eric Lowe
2000-10-11 20:59 ` Chris Evans
2000-10-11 22:10 ` Roger Larsson
2000-10-11 22:46 ` Chris Evans
2000-10-13 16:57 ` Rik van Riel
2000-10-11 18:38 ` Updated 2.4 TODO List tytso
2000-10-11 23:52 ` [RFC] atomic pte updates for x86 smp Ben LaHaise
2000-10-12 0:09 ` Linus Torvalds
2000-10-12 4:03 ` Benjamin C.R. LaHaise
2000-10-12 4:06 ` David S. Miller
2000-10-12 4:31 ` Cort Dougan [this message]
2000-10-12 4:37 ` Benjamin C.R. LaHaise
2000-10-12 6:42 ` Linus Torvalds
2000-10-12 8:13 ` Ingo Molnar
2000-10-12 8:56 ` David S. Miller
2000-10-12 10:05 ` Ingo Molnar
2000-10-12 11:10 ` Ingo Molnar
2000-10-12 15:10 ` Benjamin C.R. LaHaise
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