Re: pgd/pmd/pte and x86 kernel virtual addresses

[Timur Tabi <ttabi@interactivesi.com>]

** Reply to message from "Stephen C. Tweedie" <sct@redhat.com> on Tue, 29 Aug
2000 00:09:35 +0100


> > physical pointer.  The first is the normal virtual pointer for kernel memory,
> > and the second is the one returned by ioremap_nocache().  I was under the
> > understanding that caching is enabled on physical pages only, so it shouldn't
> > matter which virtual address I use.  Is that correct?
> 
> No.  The no-cache bit is set in the page table entry, so depends on
> the virtual address.  There is a *different* form of memory access
> control which can be used to make memory non-cachable, and that is the
> "mtrr" (Memory Type Range Register), which exists in different forms
> on all recent Intel and AMD cpus.  Mtrrs work on physical addresses,
> but that is not what ioremap_nocache() uses.

Ok, thanks!  That explains a whole lot.

Another question: is there a way I can enable Write Combining on a page,
without using MTRR's?



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Timur Tabi - ttabi@interactivesi.com
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