From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail138.messagelabs.com (mail138.messagelabs.com [216.82.249.35]) by kanga.kvack.org (Postfix) with SMTP id 2C23B6B0169 for ; Thu, 25 Aug 2011 14:34:43 -0400 (EDT) References: <1313650253-21794-1-git-send-email-gthelen@google.com> <20110818144025.8e122a67.akpm@linux-foundation.org> <1314284272.27911.32.camel@twins> <1314289208.3268.4.camel@mulgrave> <986ca4ed-6810-426f-b32f-5c8687e3a10b@email.android.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [PATCH] memcg: remove unneeded preempt_disable From: James Bottomley Date: Thu, 25 Aug 2011 11:34:34 -0700 Message-ID: <1e295500-5d1f-45dd-aa5b-3d2da2cf1a62@email.android.com> Sender: owner-linux-mm@kvack.org List-ID: To: Christoph Lameter Cc: Peter Zijlstra , Andrew Morton , Greg Thelen , linux-kernel@vger.kernel.org, linux-mm@kvack.org, KAMEZAWA Hiroyuki , Balbir Singh , Daisuke Nishimura , linux-arch@vger.kernel.org Christoph Lameter wrote: >On Thu, 25 Aug 2011, James Bottomley wrote: > >> >ARM seems to have these LDREX/STREX instructions for that purpose >which >> >seem to be used for generating atomic instructions without lockes. I >> >guess >> >other RISC architectures have similar means of doing it? >> >> Arm isn't really risc. Most don't. However even with ldrex/strex >you need two instructions for rmw. > >Well then what is "really risc"? RISC is an old beaten down marketing >term >AFAICT and ARM claims it too. Reduced Instruction Set Computer. This is why we're unlikely to have complex atomic instructions: the principle of risc is that you build them up from basic ones. James -- Sent from my Android phone with K-9 Mail. Please excuse my brevity and top posting. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Fight unfair telecom internet charges in Canada: sign http://stopthemeter.ca/ Don't email: email@kvack.org