* vremap question
@ 1999-08-12 14:19 Gilles Pokam
1999-08-12 14:41 ` Benjamin C.R. LaHaise
0 siblings, 1 reply; 2+ messages in thread
From: Gilles Pokam @ 1999-08-12 14:19 UTC (permalink / raw)
To: linux-mm
Hi,
Are there some restrictions on the use of vremap ?
I am trying to map 1MB of my PCI-device memory into kernel space. Having the base
i/o address and the span of my device memory i use the ioremap function like this:
virt = ioremap_nocache(base_io,size);
my device memory is subdivided like this: 216kb of unused memory,216kb of prom,128kb
register,128kb fpga and 216kb of sram. After the ioremap call, i can access the prom
region, but any attempt to read or write the sram,register or fpga region yields 0x0!
can someone tell me what is wrong ?
Thanks.
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* Re: vremap question
1999-08-12 14:19 vremap question Gilles Pokam
@ 1999-08-12 14:41 ` Benjamin C.R. LaHaise
0 siblings, 0 replies; 2+ messages in thread
From: Benjamin C.R. LaHaise @ 1999-08-12 14:41 UTC (permalink / raw)
To: Gilles Pokam; +Cc: linux-mm
On Thu, 12 Aug 1999, Gilles Pokam wrote:
> Are there some restrictions on the use of vremap ?
>
> I am trying to map 1MB of my PCI-device memory into kernel space. Having the base
> i/o address and the span of my device memory i use the ioremap function like this:
> virt = ioremap_nocache(base_io,size);
That sounds right so long as your base address and size are page aligned.
> my device memory is subdivided like this: 216kb of unused memory,216kb of prom,128kb
> register,128kb fpga and 216kb of sram. After the ioremap call, i can access the prom
> region, but any attempt to read or write the sram,register or fpga region yields 0x0!
>
> can someone tell me what is wrong ?
If ioremap returned non-NULL, then it is successful. Are you certain
about the memory mapping? If this sounds like a new piece of hardware, I
wouldn't bet the farm on it working properly at all. The fact that you're
reading 0's means that something is responding on the bus, but that
doesn't mean the timing is right -- one device I worked on would randomly
report 0s or garbage on reads of large blocks until the FPGA code was
right.
-ben
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