From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by kanga.kvack.org (Postfix) with ESMTP id 7978E6B0710 for ; Fri, 9 Nov 2018 12:28:42 -0500 (EST) Received: by mail-pg1-f197.google.com with SMTP id 202so1006065pgb.6 for ; Fri, 09 Nov 2018 09:28:42 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com. [134.134.136.65]) by mx.google.com with ESMTPS id d17si7536758pgl.484.2018.11.09.09.28.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Nov 2018 09:28:41 -0800 (PST) Subject: Re: [PATCH v5 04/27] x86/fpu/xstate: Add XSAVES system states for shadow stack From: Dave Hansen References: <20181011151523.27101-1-yu-cheng.yu@intel.com> <20181011151523.27101-5-yu-cheng.yu@intel.com> <4295b8f786c10c469870a6d9725749ce75dcdaa2.camel@intel.com> <043a17ef-dc9f-56d2-5fba-1a58b7b0fd4d@intel.com> <20181108220054.GP3074@bombadil.infradead.org> <20181109003225.GQ3074@bombadil.infradead.org> <6cd2ae51-2d2a-9c68-df7c-45b49e0a813f@intel.com> <20181109171740.GT3074@bombadil.infradead.org> Message-ID: <1851ca3a-6470-7a9c-1aeb-930527458e16@intel.com> Date: Fri, 9 Nov 2018 09:28:40 -0800 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Matthew Wilcox Cc: Andy Lutomirski , Yu-cheng Yu , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , LKML , "open list:DOCUMENTATION" , Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H. J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , "Shanbhogue, Vedvyas" On 11/9/18 9:20 AM, Dave Hansen wrote: > On 11/9/18 9:17 AM, Matthew Wilcox wrote: >>> But, later versions of the hardware have instructions that don't have >>> static offsets for the state components (when the XSAVES/XSAVEC >>> instructions are used). So, for those, the structure embedding isn't >>> used at *all* since some state might not be present. >> But *when present*, this structure is always aligned on an 8-byte >> boundary, right? Practically, though, I think it ends up always being aligned on an 8-byte boundary.