From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dave.hansen@linux.intel.com, linux-mm@kvack.org,
linux-acpi@vger.kernel.org
Subject: [PATCH 05/18] cxl/region: Add volatile region creation support
Date: Sun, 05 Feb 2023 17:02:56 -0800 [thread overview]
Message-ID: <167564537678.847146.4066579806086171091.stgit@dwillia2-xfh.jf.intel.com> (raw)
In-Reply-To: <167564534874.847146.5222419648551436750.stgit@dwillia2-xfh.jf.intel.com>
Expand the region creation infrastructure to enable 'ram'
(volatile-memory) regions. The internals of create_pmem_region_store()
and create_pmem_region_show() are factored out into helpers
__create_region() and __create_region_show() for the 'ram' case to
reuse.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
Documentation/ABI/testing/sysfs-bus-cxl | 22 +++++-----
drivers/cxl/core/core.h | 1
drivers/cxl/core/port.c | 14 ++++++
drivers/cxl/core/region.c | 71 +++++++++++++++++++++++++------
4 files changed, 82 insertions(+), 26 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index 4c4e1cbb1169..3acf2f17a73f 100644
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl
@@ -285,20 +285,20 @@ Description:
interleave_granularity).
-What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region
-Date: May, 2022
-KernelVersion: v6.0
+What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region
+Date: May, 2022, January, 2023
+KernelVersion: v6.0 (pmem), v6.3 (ram)
Contact: linux-cxl@vger.kernel.org
Description:
(RW) Write a string in the form 'regionZ' to start the process
- of defining a new persistent memory region (interleave-set)
- within the decode range bounded by root decoder 'decoderX.Y'.
- The value written must match the current value returned from
- reading this attribute. An atomic compare exchange operation is
- done on write to assign the requested id to a region and
- allocate the region-id for the next creation attempt. EBUSY is
- returned if the region name written does not match the current
- cached value.
+ of defining a new persistent, or volatile memory region
+ (interleave-set) within the decode range bounded by root decoder
+ 'decoderX.Y'. The value written must match the current value
+ returned from reading this attribute. An atomic compare exchange
+ operation is done on write to assign the requested id to a
+ region and allocate the region-id for the next creation attempt.
+ EBUSY is returned if the region name written does not match the
+ current cached value.
What: /sys/bus/cxl/devices/decoderX.Y/delete_region
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 8c04672dca56..5eb873da5a30 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -11,6 +11,7 @@ extern struct attribute_group cxl_base_attribute_group;
#ifdef CONFIG_CXL_REGION
extern struct device_attribute dev_attr_create_pmem_region;
+extern struct device_attribute dev_attr_create_ram_region;
extern struct device_attribute dev_attr_delete_region;
extern struct device_attribute dev_attr_region;
extern const struct device_type cxl_pmem_region_type;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 8566451cb22f..47e450c3a5a9 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -294,6 +294,7 @@ static struct attribute *cxl_decoder_root_attrs[] = {
&dev_attr_cap_type3.attr,
&dev_attr_target_list.attr,
SET_CXL_REGION_ATTR(create_pmem_region)
+ SET_CXL_REGION_ATTR(create_ram_region)
SET_CXL_REGION_ATTR(delete_region)
NULL,
};
@@ -305,6 +306,13 @@ static bool can_create_pmem(struct cxl_root_decoder *cxlrd)
return (cxlrd->cxlsd.cxld.flags & flags) == flags;
}
+static bool can_create_ram(struct cxl_root_decoder *cxlrd)
+{
+ unsigned long flags = CXL_DECODER_F_TYPE3 | CXL_DECODER_F_RAM;
+
+ return (cxlrd->cxlsd.cxld.flags & flags) == flags;
+}
+
static umode_t cxl_root_decoder_visible(struct kobject *kobj, struct attribute *a, int n)
{
struct device *dev = kobj_to_dev(kobj);
@@ -313,7 +321,11 @@ static umode_t cxl_root_decoder_visible(struct kobject *kobj, struct attribute *
if (a == CXL_REGION_ATTR(create_pmem_region) && !can_create_pmem(cxlrd))
return 0;
- if (a == CXL_REGION_ATTR(delete_region) && !can_create_pmem(cxlrd))
+ if (a == CXL_REGION_ATTR(create_ram_region) && !can_create_ram(cxlrd))
+ return 0;
+
+ if (a == CXL_REGION_ATTR(delete_region) &&
+ !(can_create_pmem(cxlrd) || can_create_ram(cxlrd)))
return 0;
return a->mode;
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 53d6dbe4de6d..8dea49c021b8 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1685,6 +1685,15 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd,
struct device *dev;
int rc;
+ switch (mode) {
+ case CXL_DECODER_RAM:
+ case CXL_DECODER_PMEM:
+ break;
+ default:
+ dev_err(&cxlrd->cxlsd.cxld.dev, "unsupported mode %d\n", mode);
+ return ERR_PTR(-EINVAL);
+ }
+
cxlr = cxl_region_alloc(cxlrd, id);
if (IS_ERR(cxlr))
return cxlr;
@@ -1713,12 +1722,38 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd,
return ERR_PTR(rc);
}
+static ssize_t __create_region_show(struct cxl_root_decoder *cxlrd, char *buf)
+{
+ return sysfs_emit(buf, "region%u\n", atomic_read(&cxlrd->region_id));
+}
+
static ssize_t create_pmem_region_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
- struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
+ return __create_region_show(to_cxl_root_decoder(dev), buf);
+}
- return sysfs_emit(buf, "region%u\n", atomic_read(&cxlrd->region_id));
+static ssize_t create_ram_region_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return __create_region_show(to_cxl_root_decoder(dev), buf);
+}
+
+static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd,
+ enum cxl_decoder_mode mode, int id)
+{
+ int rc;
+
+ rc = memregion_alloc(GFP_KERNEL);
+ if (rc < 0)
+ return ERR_PTR(rc);
+
+ if (atomic_cmpxchg(&cxlrd->region_id, id, rc) != id) {
+ memregion_free(rc);
+ return ERR_PTR(-EBUSY);
+ }
+
+ return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_EXPANDER);
}
static ssize_t create_pmem_region_store(struct device *dev,
@@ -1727,29 +1762,37 @@ static ssize_t create_pmem_region_store(struct device *dev,
{
struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
struct cxl_region *cxlr;
- int id, rc;
+ int rc, id;
rc = sscanf(buf, "region%d\n", &id);
if (rc != 1)
return -EINVAL;
- rc = memregion_alloc(GFP_KERNEL);
- if (rc < 0)
- return rc;
+ cxlr = __create_region(cxlrd, CXL_DECODER_PMEM, id);
+ if (IS_ERR(cxlr))
+ return PTR_ERR(cxlr);
+ return len;
+}
+DEVICE_ATTR_RW(create_pmem_region);
- if (atomic_cmpxchg(&cxlrd->region_id, id, rc) != id) {
- memregion_free(rc);
- return -EBUSY;
- }
+static ssize_t create_ram_region_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
+ struct cxl_region *cxlr;
+ int rc, id;
- cxlr = devm_cxl_add_region(cxlrd, id, CXL_DECODER_PMEM,
- CXL_DECODER_EXPANDER);
+ rc = sscanf(buf, "region%d\n", &id);
+ if (rc != 1)
+ return -EINVAL;
+
+ cxlr = __create_region(cxlrd, CXL_DECODER_RAM, id);
if (IS_ERR(cxlr))
return PTR_ERR(cxlr);
-
return len;
}
-DEVICE_ATTR_RW(create_pmem_region);
+DEVICE_ATTR_RW(create_ram_region);
static ssize_t region_show(struct device *dev, struct device_attribute *attr,
char *buf)
next prev parent reply other threads:[~2023-02-06 1:03 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 1:02 [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Dan Williams
2023-02-06 1:02 ` [PATCH 01/18] cxl/Documentation: Update references to attributes added in v6.0 Dan Williams
2023-02-06 15:17 ` Jonathan Cameron
2023-02-06 16:37 ` Gregory Price
2023-02-06 17:27 ` [PATCH 1/18] " Davidlohr Bueso
2023-02-06 19:15 ` [PATCH 01/18] " Ira Weiny
2023-02-06 21:04 ` Dave Jiang
2023-02-09 0:20 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 02/18] cxl/region: Add a mode attribute for regions Dan Williams
2023-02-06 15:46 ` Jonathan Cameron
2023-02-06 17:47 ` Dan Williams
2023-02-06 16:39 ` Gregory Price
2023-02-06 19:16 ` Ira Weiny
2023-02-06 21:05 ` Dave Jiang
2023-02-09 0:22 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 03/18] cxl/region: Support empty uuids for non-pmem regions Dan Williams
2023-02-06 15:54 ` Jonathan Cameron
2023-02-06 18:07 ` Dan Williams
2023-02-06 19:22 ` Ira Weiny
2023-02-06 19:35 ` Dan Williams
2023-02-09 0:24 ` Verma, Vishal L
2023-02-06 1:02 ` [PATCH 04/18] cxl/region: Validate region mode vs decoder mode Dan Williams
2023-02-06 16:02 ` Jonathan Cameron
2023-02-06 18:14 ` Dan Williams
2023-02-06 16:44 ` Gregory Price
2023-02-06 21:51 ` Dan Williams
2023-02-06 19:55 ` Gregory Price
2023-02-06 19:23 ` Ira Weiny
2023-02-06 22:16 ` Dave Jiang
2023-02-09 0:25 ` Verma, Vishal L
2023-02-06 1:02 ` Dan Williams [this message]
2023-02-06 16:18 ` [PATCH 05/18] cxl/region: Add volatile region creation support Jonathan Cameron
2023-02-06 18:19 ` Dan Williams
2023-02-06 16:55 ` Gregory Price
2023-02-06 21:57 ` Dan Williams
2023-02-06 19:56 ` Gregory Price
2023-02-06 19:25 ` Ira Weiny
2023-02-06 22:31 ` Dave Jiang
2023-02-06 22:37 ` Dan Williams
2023-02-09 1:02 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 06/18] cxl/region: Refactor attach_target() for autodiscovery Dan Williams
2023-02-06 17:06 ` Jonathan Cameron
2023-02-06 18:48 ` Dan Williams
2023-02-06 19:26 ` Ira Weiny
2023-02-06 22:41 ` Dave Jiang
2023-02-09 1:09 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 07/18] cxl/region: Move region-position validation to a helper Dan Williams
2023-02-06 17:44 ` Ira Weiny
2023-02-06 19:15 ` Dan Williams
2023-02-08 12:30 ` Jonathan Cameron
2023-02-09 4:09 ` Dan Williams
2023-02-09 4:26 ` Dan Williams
2023-02-09 11:07 ` Jonathan Cameron
2023-02-09 20:52 ` Dan Williams
2023-02-09 19:45 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 08/18] kernel/range: Uplevel the cxl subsystem's range_contains() helper Dan Williams
2023-02-06 17:02 ` Gregory Price
2023-02-06 22:01 ` Dan Williams
2023-02-06 19:28 ` Ira Weiny
2023-02-06 23:41 ` Dave Jiang
2023-02-08 12:32 ` Jonathan Cameron
2023-02-09 19:47 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 09/18] cxl/region: Enable CONFIG_CXL_REGION to be toggled Dan Williams
2023-02-06 17:03 ` Gregory Price
2023-02-06 23:57 ` Dave Jiang
2023-02-08 12:36 ` Jonathan Cameron
2023-02-09 20:17 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 10/18] cxl/region: Fix passthrough-decoder detection Dan Williams
2023-02-06 5:38 ` Greg KH
2023-02-06 17:22 ` Dan Williams
2023-02-07 0:00 ` Dave Jiang
2023-02-08 12:44 ` Jonathan Cameron
2023-02-09 20:28 ` Verma, Vishal L
2023-02-06 1:03 ` [PATCH 11/18] cxl/region: Add region autodiscovery Dan Williams
2023-02-06 19:02 ` Ira Weiny
2023-02-07 23:54 ` Dave Jiang
2023-02-08 17:07 ` Jonathan Cameron
2023-02-09 4:07 ` Dan Williams
2023-02-06 1:03 ` [PATCH 12/18] tools/testing/cxl: Define a fixed volatile configuration to parse Dan Williams
2023-02-08 17:31 ` Jonathan Cameron
2023-02-09 20:50 ` Dan Williams
2023-02-06 1:03 ` [PATCH 13/18] dax/hmem: Move HMAT and Soft reservation probe initcall level Dan Williams
2023-02-06 1:03 ` [PATCH 14/18] dax/hmem: Drop unnecessary dax_hmem_remove() Dan Williams
2023-02-06 17:15 ` Gregory Price
2023-02-08 17:33 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 15/18] dax/hmem: Convey the dax range via memregion_info() Dan Williams
2023-02-08 17:35 ` Jonathan Cameron
2023-02-06 1:03 ` [PATCH 16/18] dax/hmem: Move hmem device registration to dax_hmem.ko Dan Williams
2023-02-06 1:04 ` [PATCH 17/18] dax: Assign RAM regions to memory-hotplug by default Dan Williams
2023-02-06 17:26 ` Gregory Price
2023-02-06 22:15 ` Dan Williams
2023-02-06 19:05 ` Gregory Price
2023-02-06 23:20 ` Dan Williams
2023-02-06 1:04 ` [PATCH 18/18] cxl/dax: Create dax devices for CXL RAM regions Dan Williams
2023-02-06 5:36 ` [PATCH 00/18] CXL RAM and the 'Soft Reserved' => 'System RAM' default Gregory Price
2023-02-06 16:40 ` Davidlohr Bueso
2023-02-06 18:23 ` Dan Williams
2023-02-06 17:29 ` Dan Williams
2023-02-06 17:18 ` Davidlohr Bueso
[not found] ` <CGME20230208173730uscas1p2af3a9eeb8946dfa607b190c079a49653@uscas1p2.samsung.com>
2023-02-08 17:37 ` Fan Ni
2023-02-09 4:56 ` Dan Williams
2023-02-13 12:13 ` David Hildenbrand
2023-02-14 18:45 ` Dan Williams
2023-02-14 18:27 ` Gregory Price
2023-02-14 18:39 ` Dan Williams
2023-02-14 19:01 ` Gregory Price
2023-02-14 21:18 ` Jonathan Cameron
2023-02-14 21:51 ` Gregory Price
2023-02-14 21:54 ` Gregory Price
2023-02-15 10:03 ` Jonathan Cameron
2023-02-18 9:47 ` Gregory Price
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