From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F60C433EF for ; Thu, 4 Nov 2021 08:34:43 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id DCC546120E for ; Thu, 4 Nov 2021 08:34:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DCC546120E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linuxfoundation.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvack.org Received: by kanga.kvack.org (Postfix) id 3F9BF940007; Thu, 4 Nov 2021 04:34:42 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 3A90F6B0072; Thu, 4 Nov 2021 04:34:42 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 2709F940007; Thu, 4 Nov 2021 04:34:42 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0002.hostedemail.com [216.40.44.2]) by kanga.kvack.org (Postfix) with ESMTP id 14D766B006C for ; Thu, 4 Nov 2021 04:34:42 -0400 (EDT) Received: from smtpin01.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id C4CF074D14 for ; Thu, 4 Nov 2021 08:34:41 +0000 (UTC) X-FDA: 78770586804.01.F813CE3 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by imf07.hostedemail.com (Postfix) with ESMTP id 4DF4410000B8 for ; Thu, 4 Nov 2021 08:34:41 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 6B6A0610FC; Thu, 4 Nov 2021 08:34:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1636014880; bh=55aln/7sj59GYMCgR0T0A++FszGtx/Qjba6ZHcPI76Y=; h=Subject:To:Cc:From:Date:In-Reply-To:From; b=S63iroAHEmHUm/OYxGipwMrY49ertwpedf1Ik0SyfBjpI97EFbNgBHUMjw+leozFl VF3upxWfNaRuwCKgpb6euY9dpCiBv+IQKYzKptnUVOBj6hFSoa+AA6MQylW1LVluXK Y7wDusfUi5NxeJh+DQ2CKlu1uIB21aTbDqpsbInQ= Subject: Patch "arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed" has been added to the 4.9-stable tree To: arnd@arndb.de,benh@kernel.crashing.org,f.fainelli@gmail.com,gregkh@linuxfoundation.org,hpa@zytor.com,kirill.shutemov@linux.intel.com,linux-arm-kernel@lists.infradead.org,linux-mips@linux-mips.org,linux-mm@kvack.org,linux-snps-arc@lists.infradead.org,linux@armlinux.org.uk,linuxppc-dev@lists.ozlabs.org,minchan@kernel.org,mingo@redhat.com,mpe@ellerman.id.au,ngupta@vflare.org,paulus@samba.org,ralf@linux-mips.org,rppt@linux.ibm.com,sashal@kernel.org,sergey.senozhatsky.work@gmail.com,stefan@agner.ch,tglx@linutronix.de,tsbogend@alpha.franken.de,vgupta@synopsys.com,x86@kernel.org Cc: From: Date: Thu, 04 Nov 2021 09:34:37 +0100 In-Reply-To: <20211103205714.374801-3-f.fainelli@gmail.com> Message-ID: <1636014877194230@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 X-stable: commit X-Patchwork-Hint: ignore X-Rspamd-Queue-Id: 4DF4410000B8 X-Stat-Signature: t9jczwjr7zf15tn16sidfdb3m5d5utg5 Authentication-Results: imf07.hostedemail.com; dkim=fail ("body hash did not verify") header.d=linuxfoundation.org header.s=korg header.b=S63iroAH; dmarc=pass (policy=none) header.from=linuxfoundation.org; spf=pass (imf07.hostedemail.com: domain of gregkh@linuxfoundation.org designates 198.145.29.99 as permitted sender) smtp.mailfrom=gregkh@linuxfoundation.org X-Rspamd-Server: rspam01 X-HE-Tag: 1636014881-828209 Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: This is a note to let you know that I've just added the patch titled arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed to the 4.9-stable tree which can be found at: http://www.kernel.org/git/?p=3Dlinux/kernel/git/stable/stable-queue.g= it;a=3Dsummary The filename of the patch is: arch-pgtable-define-max_possible_physmem_bits-where-needed.patch and it can be found in the queue-4.9 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >From foo@baz Thu Nov 4 09:33:49 AM CET 2021 From: Florian Fainelli Date: Wed, 3 Nov 2021 13:57:14 -0700 Subject: arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed To: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org, Greg Kroah-Hartman , Sasha Levin , Arnd Bergmann , Thoma= s Bogendoerfer , Stefan Agner , Mike Rapoport , Florian Fainelli , Vineet Gupta , Russell King , Ralf Baechle , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman= , Thomas Gleixner , Ingo Molnar = , "H. Peter Anvin" , x86@kernel.org (mai= ntainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Minchan Kim , Nitin Gupta , Sergey Senozhatsky , "Kirill A. Shutemov" , linux-snps-arc@lists.infradead.org (open list:SYNOPSYS ARC ARCHITE= CTURE), linux-arm-kernel@lists.infradead.org (mod erated list:ARM PORT), linux-mips@linux-mips.org (open list:MIPS), linux= ppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)= ), linux-arch@vger.kernel.org (open list:GENERIC INCLUDE/ASM HEADER FILES= ), linux-mm@kvack.org (open list:ZSMALLOC COMPRESSED SLAB MEMORY ALLOCATO= R) Message-ID: <20211103205714.374801-3-f.fainelli@gmail.com> From: Arnd Bergmann [ Upstream commit cef397038167ac15d085914493d6c86385773709 ] Stefan Agner reported a bug when using zsram on 32-bit Arm machines with RAM above the 4GB address boundary: Unable to handle kernel NULL pointer dereference at virtual address 000= 00000 pgd =3D a27bd01c [00000000] *pgd=3D236a0003, *pmd=3D1ffa64003 Internal error: Oops: 207 [#1] SMP ARM Modules linked in: mdio_bcm_unimac(+) brcmfmac cfg80211 brcmutil raspbe= rrypi_hwmon hci_uart crc32_arm_ce bcm2711_thermal phy_generic genet CPU: 0 PID: 123 Comm: mkfs.ext4 Not tainted 5.9.6 #1 Hardware name: BCM2711 PC is at zs_map_object+0x94/0x338 LR is at zram_bvec_rw.constprop.0+0x330/0xa64 pc : [] lr : [] psr: 60000013 sp : e376bbe0 ip : 00000000 fp : c1e2921c r10: 00000002 r9 : c1dda730 r8 : 00000000 r7 : e8ff7a00 r6 : 00000000 r5 : 02f9ffa0 r4 : e3710000 r3 : 000fdffe r2 : c1e0ce80 r1 : ebf979a0 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 30c5383d Table: 235c2a80 DAC: fffffffd Process mkfs.ext4 (pid: 123, stack limit =3D 0x495a22e6) Stack: (0xe376bbe0 to 0xe376c000) As it turns out, zsram needs to know the maximum memory size, which is defined in MAX_PHYSMEM_BITS when CONFIG_SPARSEMEM is set, or in MAX_POSSIBLE_PHYSMEM_BITS on the x86 architecture. The same problem will be hit on all 32-bit architectures that have a physical address space larger than 4GB and happen to not enable sparsemem and include asm/sparsemem.h from asm/pgtable.h. After the initial discussion, I suggested just always defining MAX_POSSIBLE_PHYSMEM_BITS whenever CONFIG_PHYS_ADDR_T_64BIT is set, or provoking a build error otherwise. This addresses all configurations that can currently have this runtime bug, but leaves all other configurations unchanged. I looked up the possible number of bits in source code and datasheets, here is what I found: - on ARC, CONFIG_ARC_HAS_PAE40 controls whether 32 or 40 bits are used - on ARM, CONFIG_LPAE enables 40 bit addressing, without it we never support more than 32 bits, even though supersections in theory allow up to 40 bits as well. - on MIPS, some MIPS32r1 or later chips support 36 bits, and MIPS32r5 XPA supports up to 60 bits in theory, but 40 bits are more than anyone will ever ship - On PowerPC, there are three different implementations of 36 bit addressing, but 32-bit is used without CONFIG_PTE_64BIT - On RISC-V, the normal page table format can support 34 bit addressing. There is no highmem support on RISC-V, so anything above 2GB is unused, but it might be useful to eventually support CONFIG_ZRAM for high pages. Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation libra= ry") Fixes: 02390b87a945 ("mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS") Acked-by: Thomas Bogendoerfer Reviewed-by: Stefan Agner Tested-by: Stefan Agner Acked-by: Mike Rapoport Link: https://lore.kernel.org/linux-mm/bdfa44bf1c570b05d6c70898e2bbb0acf2= 34ecdf.1604762181.git.stefan@agner.ch/ Signed-off-by: Arnd Bergmann Signed-off-by: Sasha Levin [florian: patch arch/powerpc/include/asm/pte-common.h for 4.9.y removed arch/riscv/include/asm/pgtable.h which does not exist] Signed-off-by: Florian Fainelli Signed-off-by: Greg Kroah-Hartman --- arch/arc/include/asm/pgtable.h | 2 ++ arch/arm/include/asm/pgtable-2level.h | 2 ++ arch/arm/include/asm/pgtable-3level.h | 2 ++ arch/mips/include/asm/pgtable-32.h | 3 +++ arch/powerpc/include/asm/pte-common.h | 2 ++ include/asm-generic/pgtable.h | 13 +++++++++++++ 6 files changed, 24 insertions(+) --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -137,8 +137,10 @@ =20 #ifdef CONFIG_ARC_HAS_PAE40 #define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 | PAGE_MASK | _PAGE_CACHEA= BLE) +#define MAX_POSSIBLE_PHYSMEM_BITS 40 #else #define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE) +#define MAX_POSSIBLE_PHYSMEM_BITS 32 #endif =20 /***********************************************************************= *** --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -78,6 +78,8 @@ #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) =20 +#define MAX_POSSIBLE_PHYSMEM_BITS 32 + /* * PMD_SHIFT determines the size of the area a second-level page table c= an map * PGDIR_SHIFT determines what a third-level page table entry can map --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -37,6 +37,8 @@ #define PTE_HWTABLE_OFF (0) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) =20 +#define MAX_POSSIBLE_PHYSMEM_BITS 40 + /* * PGDIR_SHIFT determines the size a top-level page table entry can map. */ --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -110,6 +110,7 @@ static inline void pmd_clear(pmd_t *pmdp =20 #if defined(CONFIG_XPA) =20 +#define MAX_POSSIBLE_PHYSMEM_BITS 40 #define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (un= signed long)((x).pte_low << _PAGE_PRESENT_SHIFT)) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) @@ -125,6 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot =20 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) =20 +#define MAX_POSSIBLE_PHYSMEM_BITS 36 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) =20 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) @@ -139,6 +141,7 @@ static inline pte_t pfn_pte(unsigned lon =20 #else =20 +#define MAX_POSSIBLE_PHYSMEM_BITS 32 #ifdef CONFIG_CPU_VR41XX #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_va= l(prot)) --- a/arch/powerpc/include/asm/pte-common.h +++ b/arch/powerpc/include/asm/pte-common.h @@ -101,8 +101,10 @@ static inline bool pte_user(pte_t pte) */ #if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) #define PTE_RPN_MASK (~((1ULL<