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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id p24sm349875pfh.17.2021.06.15.18.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 18:44:45 -0700 (PDT) Date: Wed, 16 Jun 2021 11:44:39 +1000 From: Nicholas Piggin Subject: Re: [PATCH v7 00/11] Speedup mremap on ppc64 To: Linus Torvalds Cc: "akpm@linux-foundation.org" , "Aneesh Kumar K.V" , Christophe Leroy , "joel@joelfernandes.org" , "kaleshsingh@google.com" , "Kirill A . Shutemov" , "linux-mm@kvack.org" , "linuxppc-dev@lists.ozlabs.org" , "mpe@ellerman.id.au" References: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1623807215.t2mo6ahd0q.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Authentication-Results: imf21.hostedemail.com; dkim=pass header.d=gmail.com header.s=20161025 header.b=Vx2bn0N7; dmarc=pass (policy=none) header.from=gmail.com; spf=pass (imf21.hostedemail.com: domain of npiggin@gmail.com designates 209.85.214.179 as permitted sender) smtp.mailfrom=npiggin@gmail.com X-Stat-Signature: ykghwreqzp5kuyeqw19ta77gauwobu95 X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 36058E000255 X-HE-Tag: 1623807874-971891 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Excerpts from Linus Torvalds's message of June 9, 2021 3:10 am: > On Mon, Jun 7, 2021 at 3:10 AM Nick Piggin wrote: >> >> I'd really rather not do this, I'm not sure if micro benchmark captures = everything. >=20 > I don't much care what powerpc code does _itnernally_ for this > architecture-specific mis-design issue, but I really don't want to see > more complex generic interfaces unless you have better hard numbers > for them. >=20 > So far the numbers are: "no observable difference". >=20 > It would have to be not just observable, but actually meaningful for > me to go "ok, we'll add this crazy flag that nobody else cares about". Fair enough, will have to try get more numbers then I suppose. >=20 > And honestly, from everything I've seen on page table walker caches: > they are great, but once you start remapping big ranges and > invallidating megabytes of TLB's, the walker caches just aren't going > to be your issue. Remapping big ranges is going to have to invalidate intermediate caches (aka PWC), so is unmapping. So we're stuck with the big hammer PWC=20 invalidate there anyway. It's mprotect and friends that would care here, possibly some THP thing... but I guess those are probably down the list a little way. I'm a bit less concerned about the PWCs that might be caching the regions of the big mprotect() we just did, and more concerned about the effect=20 of flushing all unrelated caches. Including on all other CPUs a threaded program is running on. HANA, Java, are threaded and do mremaps,=20 unfortunately. >=20 > But: numbers talk. I'd take the sane generic interfaces as a first > cut. If somebody then has really compelling numbers, we can _then_ > look at that "optimize for odd page table walker cache situation" > case. Yep okay. It's not the end of the world (or if it is we'd be able to get numbers presumably). > And in the meantime, maybe you can talk to the hardware people and > tell them that you want the "flush range" capability to work right, > and that if the walker cache is so important they shouldn't > have made it a all-or-nothing flush. I have, more than once :( Fixing that would fix munmap etc cases as well, so yeah. Thanks, Nick