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Miller" , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org References: <20200828100022.1099682-1-npiggin@gmail.com> <20200828100022.1099682-2-npiggin@gmail.com> <20200828111525.GX1362448@hirez.programming.kicks-ass.net> In-Reply-To: <20200828111525.GX1362448@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Message-Id: <1598836589.75k5wmftvn.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Rspamd-Queue-Id: DE4AA18086CB5 X-Spamd-Result: default: False [0.00 / 100.00] X-Rspamd-Server: rspam03 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Excerpts from peterz@infradead.org's message of August 28, 2020 9:15 pm: > On Fri, Aug 28, 2020 at 08:00:19PM +1000, Nicholas Piggin wrote: >=20 >> Closing this race only requires interrupts to be disabled while ->mm >> and ->active_mm are being switched, but the TLB problem requires also >> holding interrupts off over activate_mm. Unfortunately not all archs >> can do that yet, e.g., arm defers the switch if irqs are disabled and >> expects finish_arch_post_lock_switch() to be called to complete the >> flush; um takes a blocking lock in activate_mm(). >=20 > ARM at least has activate_mm() :=3D switch_mm(), so it could be made to > work. > Yeah, so long as that post_lock_switch switch did the right thing with respect to its TLB flushing. It should do because arm doesn't seem to check ->mm or ->active_mm (and if it was broken, the scheduler context switch would be suspect too). I don't think the fix would be hard, just that I don't have a good way to test it and qemu isn't great for testing this kind of thing. um too I think could probably defer that lock until after interrupts are enabled again. I might throw a bunch of arch conversion patches over the wall if this gets merged and try to move things along. Thanks, Nick