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[134.134.136.100]) by mx.google.com with ESMTPS id x66si35538055pfk.73.2019.01.29.06.20.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 29 Jan 2019 06:20:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of joonas.lahtinen@linux.intel.com designates 134.134.136.100 as permitted sender) client-ip=134.134.136.100; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of joonas.lahtinen@linux.intel.com designates 134.134.136.100 as permitted sender) smtp.mailfrom=joonas.lahtinen@linux.intel.com; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jan 2019 06:20:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,537,1539673200"; d="scan'208";a="110714506" Received: from jlahtine-desk.ger.corp.intel.com (HELO localhost) ([10.251.87.6]) by orsmga007.jf.intel.com with ESMTP; 29 Jan 2019 06:20:00 -0800 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: Jerome Glisse From: Joonas Lahtinen Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo In-Reply-To: <20190124153032.GA5030@redhat.com> Cc: linux-mm@kvack.org, Ralph Campbell , Jan Kara , Arnd Bergmann , kvm@vger.kernel.org, Matthew Wilcox , linux-rdma@vger.kernel.org, John Hubbard , Felix Kuehling , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , Dan Williams , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Michal Hocko , Jason Gunthorpe , Ross Zwisler , linux-fsdevel@vger.kernel.org, Paolo Bonzini , Andrew Morton , =?utf-8?q?Christian_K=C3=B6nig?= References: <20190123222315.1122-1-jglisse@redhat.com> <20190123222315.1122-9-jglisse@redhat.com> <154833175216.4120.925061299171157938@jlahtine-desk.ger.corp.intel.com> <20190124153032.GA5030@redhat.com> Message-ID: <154877159986.4387.16328989441685542244@jlahtine-desk.ger.corp.intel.com> User-Agent: alot/0.6 Subject: Re: [PATCH v4 8/9] gpu/drm/i915: optimize out the case when a range is updated to read only Date: Tue, 29 Jan 2019 16:20:00 +0200 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Quoting Jerome Glisse (2019-01-24 17:30:32) > On Thu, Jan 24, 2019 at 02:09:12PM +0200, Joonas Lahtinen wrote: > > Hi Jerome, > > = > > This patch seems to have plenty of Cc:s, but none of the right ones :) > = > So sorry, i am bad with git commands. > = > > For further iterations, I guess you could use git option --cc to make > > sure everyone gets the whole series, and still keep the Cc:s in the > > patches themselves relevant to subsystems. > = > Will do. > = > > This doesn't seem to be on top of drm-tip, but on top of your previous > > patches(?) that I had some comments about. Could you take a moment to > > first address the couple of question I had, before proceeding to discuss > > what is built on top of that base. > = > It is on top of Linus tree so roughly ~ rc3 it does not depend on any > of the previous patch i posted. You actually managed to race a point in time just when Chris rewrote much of the userptr code in drm-tip, which I didn't remember of. My bad. Still interested to hearing replies to my questions in the previous thread, if the series is still relevant. Trying to get my head around how the different aspects of HMM pan out for devices without fault handling. > I still intended to propose to remove > GUP from i915 once i get around to implement the equivalent of GUP_fast > for HMM and other bonus cookies with it. > = > The plan is once i have all mm bits properly upstream then i can propose > patches to individual driver against the proper driver tree ie following > rules of each individual device driver sub-system and Cc only people > there to avoid spamming the mm folks :) Makes sense, as we're having tons of changes in this field in i915, the churn to rebase on top of them will be substantial. Regards, Joonas PS. Are you by any chance attending FOSDEM? Would be nice to chat about this. > = > = > > = > > My reply's Message-ID is: > > 154289518994.19402.3481838548028068213@jlahtine-desk.ger.corp.intel.com > > = > > Regards, Joonas > > = > > PS. Please keep me Cc:d in the following patches, I'm keen on > > understanding the motive and benefits. > > = > > Quoting jglisse@redhat.com (2019-01-24 00:23:14) > > > From: J=C3=A9r=C3=B4me Glisse > > > = > > > When range of virtual address is updated read only and corresponding > > > user ptr object are already read only it is pointless to do anything. > > > Optimize this case out. > > > = > > > Signed-off-by: J=C3=A9r=C3=B4me Glisse > > > Cc: Christian K=C3=B6nig > > > Cc: Jan Kara > > > Cc: Felix Kuehling > > > Cc: Jason Gunthorpe > > > Cc: Andrew Morton > > > Cc: Matthew Wilcox > > > Cc: Ross Zwisler > > > Cc: Dan Williams > > > Cc: Paolo Bonzini > > > Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 > > > Cc: Michal Hocko > > > Cc: Ralph Campbell > > > Cc: John Hubbard > > > Cc: kvm@vger.kernel.org > > > Cc: dri-devel@lists.freedesktop.org > > > Cc: linux-rdma@vger.kernel.org > > > Cc: linux-fsdevel@vger.kernel.org > > > Cc: Arnd Bergmann > > > --- > > > drivers/gpu/drm/i915/i915_gem_userptr.c | 16 ++++++++++++++++ > > > 1 file changed, 16 insertions(+) > > > = > > > diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/dr= m/i915/i915_gem_userptr.c > > > index 9558582c105e..23330ac3d7ea 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem_userptr.c > > > +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c > > > @@ -59,6 +59,7 @@ struct i915_mmu_object { > > > struct interval_tree_node it; > > > struct list_head link; > > > struct work_struct work; > > > + bool read_only; > > > bool attached; > > > }; > > > = > > > @@ -119,6 +120,7 @@ static int i915_gem_userptr_mn_invalidate_range_s= tart(struct mmu_notifier *_mn, > > > container_of(_mn, struct i915_mmu_notifier, mn); > > > struct i915_mmu_object *mo; > > > struct interval_tree_node *it; > > > + bool update_to_read_only; > > > LIST_HEAD(cancelled); > > > unsigned long end; > > > = > > > @@ -128,6 +130,8 @@ static int i915_gem_userptr_mn_invalidate_range_s= tart(struct mmu_notifier *_mn, > > > /* interval ranges are inclusive, but invalidate range is exc= lusive */ > > > end =3D range->end - 1; > > > = > > > + update_to_read_only =3D mmu_notifier_range_update_to_read_onl= y(range); > > > + > > > spin_lock(&mn->lock); > > > it =3D interval_tree_iter_first(&mn->objects, range->start, e= nd); > > > while (it) { > > > @@ -145,6 +149,17 @@ static int i915_gem_userptr_mn_invalidate_range_= start(struct mmu_notifier *_mn, > > > * object if it is not in the process of being destro= yed. > > > */ > > > mo =3D container_of(it, struct i915_mmu_object, it); > > > + > > > + /* > > > + * If it is already read only and we are updating to > > > + * read only then we do not need to change anything. > > > + * So save time and skip this one. > > > + */ > > > + if (update_to_read_only && mo->read_only) { > > > + it =3D interval_tree_iter_next(it, range->sta= rt, end); > > > + continue; > > > + } > > > + > > > if (kref_get_unless_zero(&mo->obj->base.refcount)) > > > queue_work(mn->wq, &mo->work); > > > = > > > @@ -270,6 +285,7 @@ i915_gem_userptr_init__mmu_notifier(struct drm_i9= 15_gem_object *obj, > > > mo->mn =3D mn; > > > mo->obj =3D obj; > > > mo->it.start =3D obj->userptr.ptr; > > > + mo->read_only =3D i915_gem_object_is_readonly(obj); > > > mo->it.last =3D obj->userptr.ptr + obj->base.size - 1; > > > INIT_WORK(&mo->work, cancel_userptr); > > > = > > > -- = > > > 2.17.2 > > > = > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel