From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28122C43334 for ; Mon, 6 Jun 2022 05:34:21 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9E70B8D0002; Mon, 6 Jun 2022 01:34:20 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 9962E8D0001; Mon, 6 Jun 2022 01:34:20 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8355D8D0002; Mon, 6 Jun 2022 01:34:20 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 6D3488D0001 for ; Mon, 6 Jun 2022 01:34:20 -0400 (EDT) Received: from smtpin02.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 40829606E0 for ; Mon, 6 Jun 2022 05:34:20 +0000 (UTC) X-FDA: 79546695480.02.39D575A Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by imf06.hostedemail.com (Postfix) with ESMTP id 5669A18001E for ; Mon, 6 Jun 2022 05:34:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654493659; x=1686029659; h=message-id:subject:from:to:cc:date:in-reply-to: references:mime-version:content-transfer-encoding; bh=/SZSzFZ1dFhPPIgGw9fcoNgrT9yACgit2VivRF4SOag=; b=ABzenYs2ZNIxNeurT2IXBGYiHCbebkpFl1wCEkk5hX5830svfoABLJEi HvtBHTNAHxJj9esgFFiEQ3vszCbtx/YJy0188Dr4dKCdK0e93GZlKu7MG osMCVrUhyTnwGxqdmAmqG6hczt4mZ0Nw6ExgJiooRR4LaixzbGARfkKl2 UbOqHpY4xY9+Jb1+RVf1CzE+sx4Mi5Br7sNQI/oSxj4SFqxcBPZyCkDkX k52rrX9nwvEpbO/FkPT2clZtuaUf+ZzzrqGuTZkeYYJRXaABOUIXD83wn pT67ptXroeMB/xt+qaH9F4HVTVzgbbG3Mwe8afkvwmUWBTbMceLAcGefc A==; X-IronPort-AV: E=McAfee;i="6400,9594,10369"; a="274162408" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="274162408" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2022 22:34:09 -0700 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="635417555" Received: from xingguom-mobl.ccr.corp.intel.com ([10.254.213.116]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jun 2022 22:34:00 -0700 Message-ID: <143e40bcf46097d14514504518fdc1870fd8d4a1.camel@intel.com> Subject: Re: [RFC PATCH v4 1/7] mm/demotion: Add support for explicit memory tiers From: Ying Huang To: Aneesh Kumar K V Cc: Greg Thelen , Yang Shi , Davidlohr Bueso , Tim C Chen , Brice Goglin , Michal Hocko , Linux Kernel Mailing List , Hesham Almatary , Dave Hansen , Jonathan Cameron , Alistair Popple , Dan Williams , Feng Tang , Jagdish Gediya , Baolin Wang , David Rientjes , linux-mm@kvack.org, akpm@linux-foundation.org Date: Mon, 06 Jun 2022 13:33:55 +0800 In-Reply-To: References: <20220527122528.129445-1-aneesh.kumar@linux.ibm.com> <20220527122528.129445-2-aneesh.kumar@linux.ibm.com> <352ae5f408b6d7d4d3d820d68e2f2c6b494e95e1.camel@intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.3-1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Rspam-User: Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=intel.com header.s=Intel header.b=ABzenYs2; dmarc=pass (policy=none) header.from=intel.com; spf=none (imf06.hostedemail.com: domain of ying.huang@intel.com has no SPF policy when checking 192.55.52.93) smtp.mailfrom=ying.huang@intel.com X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 5669A18001E X-Stat-Signature: n6d1z6zf1u3ayd5e1bcn6gm9gabai9o6 X-HE-Tag: 1654493655-943485 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On Mon, 2022-06-06 at 09:26 +0530, Aneesh Kumar K V wrote: > On 6/6/22 8:19 AM, Ying Huang wrote: > > On Thu, 2022-06-02 at 14:07 +0800, Ying Huang wrote: > > > On Fri, 2022-05-27 at 17:55 +0530, Aneesh Kumar K.V wrote: > > > > From: Jagdish Gediya > > > > > > > > In the current kernel, memory tiers are defined implicitly via a > > > > demotion path relationship between NUMA nodes, which is created > > > > during the kernel initialization and updated when a NUMA node is > > > > hot-added or hot-removed. The current implementation puts all > > > > nodes with CPU into the top tier, and builds the tier hierarchy > > > > tier-by-tier by establishing the per-node demotion targets based > > > > on the distances between nodes. > > > > > > > > This current memory tier kernel interface needs to be improved for > > > > several important use cases, > > > > > > > > The current tier initialization code always initializes > > > > each memory-only NUMA node into a lower tier. But a memory-only > > > > NUMA node may have a high performance memory device (e.g. a DRAM > > > > device attached via CXL.mem or a DRAM-backed memory-only node on > > > > a virtual machine) and should be put into a higher tier. > > > > > > > > The current tier hierarchy always puts CPU nodes into the top > > > > tier. But on a system with HBM or GPU devices, the > > > > memory-only NUMA nodes mapping these devices should be in the > > > > top tier, and DRAM nodes with CPUs are better to be placed into the > > > > next lower tier. > > > > > > > > With current kernel higher tier node can only be demoted to selected nodes on the > > > > next lower tier as defined by the demotion path, not any other > > > > node from any lower tier. This strict, hard-coded demotion order > > > > does not work in all use cases (e.g. some use cases may want to > > > > allow cross-socket demotion to another node in the same demotion > > > > tier as a fallback when the preferred demotion node is out of > > > > space), This demotion order is also inconsistent with the page > > > > allocation fallback order when all the nodes in a higher tier are > > > > out of space: The page allocation can fall back to any node from > > > > any lower tier, whereas the demotion order doesn't allow that. > > > > > > > > The current kernel also don't provide any interfaces for the > > > > userspace to learn about the memory tier hierarchy in order to > > > > optimize its memory allocations. > > > > > > > > This patch series address the above by defining memory tiers explicitly. > > > > > > > > This patch adds below sysfs interface which is read-only and > > > > can be used to read nodes available in specific tier. > > > > > > > > /sys/devices/system/memtier/memtierN/nodelist > > > > > > > > Tier 0 is the highest tier, while tier MAX_MEMORY_TIERS - 1 is the > > > > lowest tier. The absolute value of a tier id number has no specific > > > > meaning. what matters is the relative order of the tier id numbers. > > > > > > > > All the tiered memory code is guarded by CONFIG_TIERED_MEMORY. > > > > Default number of memory tiers are MAX_MEMORY_TIERS(3). All the > > > > nodes are by default assigned to DEFAULT_MEMORY_TIER(1). > > > > > > > > Default memory tier can be read from, > > > > /sys/devices/system/memtier/default_tier > > > > > > > > Max memory tier can be read from, > > > > /sys/devices/system/memtier/max_tiers > > > > > > > > This patch implements the RFC spec sent by Wei Xu at [1]. > > > > > > > > [1] https://lore.kernel.org/linux-mm/CAAPL-u-DGLcKRVDnChN9ZhxPkfxQvz9Sb93kVoX_4J2oiJSkUw@mail.gmail.com/ > > > > > > > > Signed-off-by: Jagdish Gediya > > > > Signed-off-by: Aneesh Kumar K.V > > > > > > IMHO, we should change the kernel internal implementation firstly, then > > > implement the kerne/user space interface. That is, make memory tier > > > explicit inside kernel, then expose it to user space. > > > > Why ignore this comment for v5? If you don't agree, please respond me. > > > > I am not sure what benefit such a rearrange would bring in? Right now I > am writing the series from the point of view of introducing all the > plumbing and them switching the existing demotion logic to use the new > infrastructure. Redoing the code to hide all the userspace sysfs till we > switch the demotion logic to use the new infrastructure doesn't really > bring any additional clarity to patch review and would require me to > redo the series with a lot of conflicts across the patches in the patchset. IMHO, we shouldn't introduce regression even in the middle of a patchset. Each step should only rely on previous patches in the series to work correctly. In your current way of organization, after patch [1/7], on a system with 2 memory tiers, the user space interface will output wrong information (only 1 memory tier). So I think the correct way is to make it right inside the kenrel firstly, then expose the right information to user space. Best Regards, Huang, Ying