From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7EDBC369A2 for ; Mon, 14 Apr 2025 14:11:40 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id F21E628005E; Mon, 14 Apr 2025 10:11:37 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id ED01F280054; Mon, 14 Apr 2025 10:11:37 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DBFBD28005E; Mon, 14 Apr 2025 10:11:37 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id BB035280054 for ; Mon, 14 Apr 2025 10:11:37 -0400 (EDT) Received: from smtpin16.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id 52816C02AD for ; Mon, 14 Apr 2025 14:11:39 +0000 (UTC) X-FDA: 83332837518.16.5CB5CD3 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by imf24.hostedemail.com (Postfix) with ESMTP id 66254180013 for ; Mon, 14 Apr 2025 14:11:37 +0000 (UTC) Authentication-Results: imf24.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf24.hostedemail.com: domain of ryan.roberts@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=ryan.roberts@arm.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1744639897; a=rsa-sha256; cv=none; b=FZM40XHHUVDbOmgWEib9EtkTocjqHsR4z4v0XpWZn9FT96GgZNKQAynHRMxILCFkwQmmOY yfjO1AocOWJ6KmSWwb4IIQ+w81DODIc1ipsmGcHEZPTIec+7aEhigZhYaAbCaN75aGlBQ4 pxkVreu0DyKOKtuqB1TpbTSqLGdCWgg= ARC-Authentication-Results: i=1; imf24.hostedemail.com; dkim=none; dmarc=pass (policy=none) header.from=arm.com; spf=pass (imf24.hostedemail.com: domain of ryan.roberts@arm.com designates 217.140.110.172 as permitted sender) smtp.mailfrom=ryan.roberts@arm.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1744639897; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mkgEP5DRUDoYzY/Zmbk85d0LsDHHxryv7W5ySGLwBOo=; b=nkzuux7OQQRjQY0tDshpMfkolMaPGFbPWni0JZ91uq6Em0Ne8JWRaf2avHycaDOJJwNA6w FCUww5/DjQ2HVqKKP70+ndvF6LiMPDVmzFUTUF5iNzjKMEr3NmZfhEJiOSTfW+1GVZ8EIk 5EdUhDrY9KzIPmcb3CuXSj730+DhbZo= Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 13DDB1007; Mon, 14 Apr 2025 07:11:35 -0700 (PDT) Received: from [10.57.86.225] (unknown [10.57.86.225]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5B3583F59E; Mon, 14 Apr 2025 07:11:32 -0700 (PDT) Message-ID: <0eae5a1a-70fe-49ab-bd3e-565dcd4e97cf@arm.com> Date: Mon, 14 Apr 2025 15:11:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/5] Fix lazy mmu mode Content-Language: en-GB To: Alexander Gordeev Cc: Andrew Morton , "David S. Miller" , Andreas Larsson , Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Matthew Wilcox (Oracle)" , Catalin Marinas , linux-mm@kvack.org, sparclinux@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org References: <20250303141542.3371656-1-ryan.roberts@arm.com> <912c7a32-b39c-494f-a29c-4865cd92aeba@agordeev.local> <5b0609c9-95ee-4e48-bb6d-98f57c5d2c31@arm.com> From: Ryan Roberts In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 66254180013 X-Stat-Signature: tuxoxon75fu5zmjkzdwh994id4sowb9s X-HE-Tag: 1744639897-282082 X-HE-Meta: U2FsdGVkX187vzCktrkfuoFEhk2XD42tnxDOz0OIriXFBvsox0wY3EFkloVxDcjP5WbagD4oadjnkq6Xk+bVhP1LggCPSij+5w26AyV7SpMk/+nQTCeTij6YAYPxRwgfXjXvzvfbHi3Jj+xMQkw4sQVv06wdf9KxI/AwU7Se9iNFdp/YddEOiunKppmURW4hlZQVQqgfi2THldpZaazxy/J2IhDcUX+CxvLjf5+2kUOhEtLe/ZCsIPKv7SrGlHTSTbqJntu0cvXEY/AmN+U6tAyoXJHFA8zJ61vsO7e7WuN4cPEnsxWyJ7hallf0OFnrhdUfhykhKBwe81a7IW+Q1ivQL4AvLtsUHHplNZly0hlZ2FXKeZUKrpdUPmpBJjagZQYbCuNjfACwuNKBj9Q5IM+G63vjV+/ij5U7dZDnPTRUTyBapgOGjanwYEn3pgJfPTvT8lalUCDW8yxewanlg8HCshNB1Jo54SOC7xtLzDSHg9sGrUejaU5YLF/yO7CeJqmQ36Am9Jv7uIWA0TFwCbEBT82oFgdC0ZeC/Gj7yaG9cMJA+E1FpVu+Fg/qgv0mTetvWHIIMCxk3VwIPhEQ4LyW6bsf/qsox0cq0WJUmo9pOwtfACDztKp6D/qvjfquAablUhn9npY4RRGS4cq+yMXUIzjWRfsB7stdcROZnwkrOF3qIJwFh9cZ0btVpDNbS6+TcL2CJxVt7WkjEOkj3r8+Ml8cGQmSdroaoU0lSc5r9BfOsD4xzkfKjvY1BnZJbnuxd3tfaGVqueqNeVK/439h+6dp3KEUMFQ3Vhr6r8x9yubLWsez6eR1Jdq8nmEEcahUiLlM6Dv/61UTL1e0i9j/X7QYaaIPzrET48pcKIMobt6yNXRJtRQ8wZyIGa9ZCrji1CGHMiMZpzJl/WhWnjl+Mgmr7gLgw9IzVo2Npcxk6oeVu4YQfwD032sXq3w87Bdl5b/N70MFPUbBs0x fGLIwoO8 ubReNXPPDgwlKQAxoxizulZP6P0Catm8pLHAtXxeVdt6v+NJnO3LvzWgEXTUloubxKED1cF5LnZ+/EP41aagA1CeX6E8JEK0UVky3V167iNVJMT92Gh0UZMu3L4SBfWuSo0oE0TQqVmJL9vzOpwpncLJMqw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 14/04/2025 15:04, Alexander Gordeev wrote: > On Mon, Apr 14, 2025 at 02:22:53PM +0100, Ryan Roberts wrote: >> On 10/04/2025 17:07, Alexander Gordeev wrote: >>>> I'm planning to implement lazy mmu mode for arm64 to optimize vmalloc. As part >>>> of that, I will extend lazy mmu mode to cover kernel mappings in vmalloc table >>>> walkers. While lazy mmu mode is already used for kernel mappings in a few >>>> places, this will extend it's use significantly. >>>> >>>> Having reviewed the existing lazy mmu implementations in powerpc, sparc and x86, >>>> it looks like there are a bunch of bugs, some of which may be more likely to >>>> trigger once I extend the use of lazy mmu. >>> >>> Do you have any idea about generic code issues as result of not adhering to >>> the originally stated requirement: >>> >>> /* >>> ... >>> * the PTE updates which happen during this window. Note that using this >>> * interface requires that read hazards be removed from the code. A read >>> * hazard could result in the direct mode hypervisor case, since the actual >>> * write to the page tables may not yet have taken place, so reads though >>> * a raw PTE pointer after it has been modified are not guaranteed to be >>> * up to date. >>> ... >>> */ >>> >>> I tried to follow few code paths and at least this one does not look so good: >>> >>> copy_pte_range(..., src_pte, ...) >>> ret = copy_nonpresent_pte(..., src_pte, ...) >>> try_restore_exclusive_pte(..., src_pte, ...) // is_device_exclusive_entry(entry) >>> restore_exclusive_pte(..., ptep, ...) >>> set_pte_at(..., ptep, ...) >>> set_pte(ptep, pte); // save in lazy mmu mode >>> >>> // ret == -ENOENT >>> >>> ptent = ptep_get(src_pte); // lazy mmu save is not observed >>> ret = copy_present_ptes(..., ptent, ...); // wrong ptent used >>> >>> I am not aware whether the effort to "read hazards be removed from the code" >>> has ever been made and the generic code is safe in this regard. >>> >>> What is your take on this? >> >> Hmm, that looks like a bug to me, at least based on the stated requirements. >> Although this is not a "read through a raw PTE *pointer*", it is a ptep_get(). >> The arch code can override that so I guess it has an opportunity to flush. But I >> don't think any arches are currently doing that. >> >> Probably the simplest fix is to add arch_flush_lazy_mmu_mode() before the >> ptep_get()? > > Which would completely revert the very idea of the lazy mmu mode? > (As one would flush on every PTE page table iteration). Well yes, but this is a pretty rare path, I'm guessing? > >> It won't be a problem in practice for arm64, since the pgtables are always >> updated immediately. I just want to use these hooks to defer/batch barriers in >> certain cases. >> >> And this is a pre-existing issue for the arches that use lazy mmu with >> device-exclusive mappings, which my extending lazy mmu into vmalloc won't >> exacerbate. >> >> Would you be willing/able to submit a fix? > > Well, we have a dozen of lazy mmu cases and I would guess it is not the > only piece of code that seems affected. I was thinking about debug feature > that could help spotting all troubled locations. > > Then we could assess and decide if it is feasible to fix. Just turning the > code above into the PTE read-modify-update pattern is quite an exercise... > >> Thanks, >> Ryan