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Sat, 9 Sep 2023 15:00:08 -0400 (EDT) Message-ID: <0e101df0-397a-0d1a-0080-2e60c68c79b6@sholland.org> Date: Sat, 9 Sep 2023 14:00:06 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux ppc64le; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v3 4/4] riscv: Improve flush_tlb_kernel_range() Content-Language: en-US To: Alexandre Ghiti Cc: Andrew Jones , Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230801085402.1168351-1-alexghiti@rivosinc.com> <20230801085402.1168351-5-alexghiti@rivosinc.com> From: Samuel Holland In-Reply-To: <20230801085402.1168351-5-alexghiti@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspam-User: X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 04CB0C0016 X-Stat-Signature: o4dsc6pyq74wf31f3oa197ybtzfqnqrb X-HE-Tag: 1694286013-97539 X-HE-Meta: U2FsdGVkX18/DXlvq0Bw2Y2uH9OlK23iT/1C9WqoEJwmh5FYq2AOrEdjiCn9JdZmT2YL4cT7w5YRntFl1bcc7KzPxdyUrYKYtZFScNzmUcHJXMFog86I+f3nc2cNz4qtk6R+OR1p/SjfAk0E1tR/LF7gxvHkyEMOnxnxQAImFHnZl7rsxgJRdL9fipOVO0fpGckc3RiLcRUzSGDBDpGi7oMl5q1IKJdwsaWv0QMYGYG5xBh9KWbp8xo5v/5Z3jSPUCVXBOds2afHa17HROEaOXTVvu/RGgzNczrmBnKPYTeNdmb2i1yT3Z9vULfrSTN9rUEcGdHKvyF542CLUZDA6Ua5SfuAxC5+0kd7D7Zv5uy3O1hQ4kxANvCGwmimBj/f7pzorHDcl96uFya1scggcFYE5ClQvbDH93OyKvoFOTWFsDs3P8kBde4HOB+trl4Srfpv1LaCfPqx9gbOKfP2OaO98jUaeHNfMTS/7BxBkcGAxCbZs5VqdUAtY92Z4AfqveBd/S0UAyLdSAnfPtkE8XNZZhgemoXkC2hc4z2JpJhgMbooi6DQrHZqADwAnpV0IQXG/YH/cZ0WWd+ZH+cYEK9ZDC7qM8zAVzkRLRyU1EO6eqXYH765KJ6nrcXS6miqrmyBdV2BX6jktH79xLBm4QPhJ1xITfYBK7YlFT758KTtX4MegMRkEDeLNvPqMKXVpaGuYpLIiy0CWdcvZDcNggtAqo3E1Z03KAurremSQghOh5of0hBWPZxLgQUrrV0jlvCoaft0AKuaT88x6LLos7oG1y2T8Eq45Y/O9vi5pKARiClE5Sg5EGhW4XmBs/ZL+RAibA36Rtq297cIoI9mp8zH0q3WNts+Ll8vfiga8ZqsR+F5YSSXevCEUSovCMMft0frW065TYBHf5mCGMoS2Zqcsnw9ATssNTIqVpqmdUaPtXWX1bAwC7HVWd8R6U7VMFH+FizDprO7ZoxpDDf 2RNMiot0 TioFx5tIpD/c1zE8AHGNCRkr2iL6lswrooy1FsQ9SvK4kBGfpspA1BLQxvTekO75WD2FYia/mP73LyBAuJOC14utL/79znnuaxP95Kv66eF5l+EYbjZMKf8X5O8kgskIQmDWZZCYLOnD0SdDQFQgYLAKTFBgInXkPieSLglzWpFU9J84JNgEB5iaPeaIy5KSZndBkGZRBE8/V0TEDDD7bwVD4gbn1+za9uKVEnYd5dndPZ/9tYTyJAjuANooGCsnIbf96cKy7p4D/NgU0pnkAPrhWFzhW/yCNMzB/Xfmm/oKIPW1e1iZ66IOH+moGm0bAnI6qKIHDCu5RohO+Uz3Aeq3yoMdJD77pOhmdR/YpTxBEX9k+mKz7y12SNvm1BM+QMaGlhAIYwFPAAJUPARbgmNy1NrtuMPC2nG1eWImeVpw2XC5TUNJf17/zIhGP1WSZccOT X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Alex, On 8/1/23 03:54, Alexandre Ghiti wrote: > This function used to simply flush the whole tlb of all harts, be more > subtile and try to only flush the range. > > The problem is that we can only use PAGE_SIZE as stride since we don't know > the size of the underlying mapping and then this function will be improved > only if the size of the region to flush is < threshold * PAGE_SIZE. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > arch/riscv/include/asm/tlbflush.h | 11 +++++----- > arch/riscv/mm/tlbflush.c | 34 +++++++++++++++++++++++-------- > 2 files changed, 31 insertions(+), 14 deletions(-) > > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h > index f5c4fb0ae642..7426fdcd8ec5 100644 > --- a/arch/riscv/include/asm/tlbflush.h > +++ b/arch/riscv/include/asm/tlbflush.h > @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, > void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); > void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, > unsigned long end); > +void flush_tlb_kernel_range(unsigned long start, unsigned long end); > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, > @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma, > local_flush_tlb_all(); > } > > -#define flush_tlb_mm(mm) flush_tlb_all() > -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() > -#endif /* !CONFIG_SMP || !CONFIG_MMU */ > - > /* Flush a range of kernel pages */ > static inline void flush_tlb_kernel_range(unsigned long start, > unsigned long end) > { > - flush_tlb_all(); > + local_flush_tlb_all(); > } > > +#define flush_tlb_mm(mm) flush_tlb_all() > +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() > +#endif /* !CONFIG_SMP || !CONFIG_MMU */ > + > #endif /* _ASM_RISCV_TLBFLUSH_H */ > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 0c955c474f3a..687808013758 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -120,18 +120,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, > unsigned long size, unsigned long stride) > { > struct flush_tlb_range_data ftd; > - struct cpumask *cmask = mm_cpumask(mm); > - unsigned int cpuid; > + struct cpumask *cmask, full_cmask; > bool broadcast; > > - if (cpumask_empty(cmask)) > - return; > + if (mm) { > + unsigned int cpuid; > + > + cmask = mm_cpumask(mm); > + if (cpumask_empty(cmask)) > + return; > + > + cpuid = get_cpu(); > + /* check if the tlbflush needs to be sent to other CPUs */ > + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > + } else { > + cpumask_setall(&full_cmask); > + cmask = &full_cmask; > + broadcast = true; > + } > > - cpuid = get_cpu(); > - /* check if the tlbflush needs to be sent to other CPUs */ > - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; > if (static_branch_unlikely(&use_asid_allocator)) { > - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask; > + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0; I think the bug is here. Passing a value of 0 for the ASID is not the same as passing the ASID in register x0. Only in the latter case does the TLB flush apply to global mappings, which is what you need for flush_tlb_kernel_range(). Regards, Samuel > > if (broadcast) { > if (riscv_use_ipi_for_rfence()) { > @@ -165,7 +174,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, > } > } > > - put_cpu(); > + if (mm) > + put_cpu(); > } > > void flush_tlb_mm(struct mm_struct *mm) > @@ -196,6 +206,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, > > __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); > } > + > +void flush_tlb_kernel_range(unsigned long start, unsigned long end) > +{ > + __flush_tlb_range(NULL, start, end, PAGE_SIZE); > +} > + > #ifdef CONFIG_TRANSPARENT_HUGEPAGE > void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, > unsigned long end)