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Thu, 12 May 2022 00:12:03 +0000 Received: from [10.110.48.28] (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 17:12:02 -0700 Message-ID: <0d90390c-3624-4f93-f8bd-fb29e92237d3@nvidia.com> Date: Wed, 11 May 2022 17:12:32 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH v4] mm: fix is_pinnable_page against on cma page Content-Language: en-US From: John Hubbard To: CC: Minchan Kim , Andrew Morton , linux-mm , LKML , John Dias , "David Hildenbrand" References: <2ffa7670-04ea-bb28-28f8-93a9b9eea7e8@nvidia.com> <54b5d177-f2f4-cef2-3a68-cd3b0b276f86@nvidia.com> <8f083802-7ab0-15ec-b37d-bc9471eea0b1@nvidia.com> <20220511234534.GG1790663@paulmck-ThinkPad-P17-Gen-1> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 112bcf44-221e-4f2f-be13-08da33ac0b20 X-MS-TrafficTypeDiagnostic: BN6PR12MB1299:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2022 00:12:03.9183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 112bcf44-221e-4f2f-be13-08da33ac0b20 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1299 Authentication-Results: imf14.hostedemail.com; dkim=pass header.d=Nvidia.com header.s=selector2 header.b=Tbdt1bWB; dmarc=pass (policy=reject) header.from=nvidia.com; spf=none (imf14.hostedemail.com: domain of jhubbard@nvidia.com has no SPF policy when checking 40.107.93.45) smtp.mailfrom=jhubbard@nvidia.com X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 57B941000A8 X-Rspam-User: X-Stat-Signature: c73k9ooa7bbf4nresmt33p7ps3rga4jk X-HE-Tag: 1652314324-27954 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 5/11/22 16:57, John Hubbard wrote: > On 5/11/22 16:45, Paul E. McKenney wrote: >>> >>> Well no, because the "&" operation is a single operation on the CPU, and >>> isn't going to get split up like that. >> >> Chiming in a bit late... > > Much appreciated! > >> >> The usual way that this sort of thing causes trouble is if there is a >> single store instruction that changes the value from MIGRATE_ISOLATE >> to MIGRATE_CMA, and if the compiler decides to fetch twice, AND twice, > > Doing an AND twice for "x & constant" this definitely blows my mind. Is > nothing sacred? :) > >> and then combine the results.  This could give a zero outcome where the >> underlying variable never had the value zero. >> >> Is this sort of thing low probability? >> >> Definitely. >> >> Isn't this sort of thing prohibited? >> >> Definitely not. >> >> So what you have will likely work for at least a while longer, but it >> is not guaranteed and it forces you to think a lot harder about what >> the current implementations of the compiler can and cannot do to you. >> >> The following LWN article goes through some of the possible optimizations >> (vandalisms?) in this area: https://lwn.net/Articles/793253/ >> > > hmm, I don't think we hit any of those  cases, do we? Because here, the > "write" side is via a non-inline function that I just don't believe the > compiler is allowed to call twice. Or is it? > > Minchan's earlier summary: > > CPU 0                         CPU1 > > >                               set_pageblock_migratetype(MIGRATE_ISOLATE) > > if (get_pageblock_migrate(page) & MIGRATE_CMA) > >                               set_pageblock_migratetype(MIGRATE_CMA) > > if (get_pageblock_migrate(page) & MIGRATE_ISOLATE) > > ...where set_pageblock_migratetype() is not inline. > > thanks, Let me try to say this more clearly: I don't think that the following __READ_ONCE() statement can actually help anything, given that get_pageblock_migratetype() is non-inlined: + int __mt = get_pageblock_migratetype(page); + int mt = __READ_ONCE(__mt); + + if (mt & (MIGRATE_CMA | MIGRATE_ISOLATE)) + return false; Am I missing anything here? thanks, -- John Hubbard NVIDIA