From: Christopher Lameter <cl@linux.com>
To: Bart Van Assche <bvanassche@acm.org>
Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>,
Ming Lei <ming.lei@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Christoph Hellwig <hch@lst.de>, Ming Lei <tom.leiming@gmail.com>,
linux-block <linux-block@vger.kernel.org>,
linux-mm <linux-mm@kvack.org>,
Linux FS Devel <linux-fsdevel@vger.kernel.org>,
"open list:XFS FILESYSTEM" <linux-xfs@vger.kernel.org>,
Dave Chinner <dchinner@redhat.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Jens Axboe <axboe@kernel.dk>,
Linus Torvalds <torvalds@linux-foundation.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: Re: block: DMA alignment of IO buffer allocated from slab
Date: Mon, 24 Sep 2018 16:47:53 +0000 [thread overview]
Message-ID: <010001660c7ae798-2c446e83-392a-40bd-a89d-8da2f20dd1b8-000000@email.amazonses.com> (raw)
In-Reply-To: <1537805984.195115.14.camel@acm.org>
On Mon, 24 Sep 2018, Bart Van Assche wrote:
> That means that two buffers allocated with kmalloc() may share a cache line on
> x86-64. Since it is allowed to use a buffer allocated by kmalloc() for DMA, can
> this lead to data corruption, e.g. if the CPU writes into one buffer allocated
> with kmalloc() and a device performs a DMA write to another kmalloc() buffer and
> both write operations affect the same cache line?
The devices writes to the cacheline through the processor which serializes
access appropriately.
The DMA device cannot write directly to memory after all on current Intel
processors. Other architectures have bus protocols that prevent situations
like that.
next prev parent reply other threads:[~2018-09-24 16:47 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-19 9:15 Ming Lei
2018-09-19 9:41 ` Vitaly Kuznetsov
2018-09-19 10:02 ` Ming Lei
2018-09-19 11:15 ` Vitaly Kuznetsov
2018-09-20 1:28 ` Ming Lei
2018-09-20 3:59 ` Yang Shi
2018-09-20 6:32 ` Christoph Hellwig
2018-09-20 6:31 ` Christoph Hellwig
2018-09-21 13:04 ` Vitaly Kuznetsov
2018-09-21 13:05 ` Christoph Hellwig
2018-09-21 15:00 ` Jens Axboe
2018-09-24 16:06 ` Christopher Lameter
2018-09-24 17:49 ` Jens Axboe
2018-09-24 18:00 ` Christopher Lameter
2018-09-24 18:09 ` Jens Axboe
2018-09-25 7:49 ` Dave Chinner
2018-09-25 15:44 ` Jens Axboe
2018-09-25 21:04 ` Matthew Wilcox
2018-09-23 22:42 ` Ming Lei
2018-09-24 9:46 ` Andrey Ryabinin
2018-09-24 14:19 ` Bart Van Assche
2018-09-24 14:43 ` Andrey Ryabinin
2018-09-24 15:08 ` Bart Van Assche
2018-09-24 15:52 ` Andrey Ryabinin
2018-09-24 15:58 ` Bart Van Assche
2018-09-24 16:07 ` Andrey Ryabinin
2018-09-24 16:19 ` Bart Van Assche
2018-09-24 16:47 ` Christopher Lameter [this message]
2018-09-24 18:57 ` Matthew Wilcox
2018-09-24 19:56 ` Bart Van Assche
2018-09-24 20:41 ` Matthew Wilcox
2018-09-24 20:54 ` Bart Van Assche
2018-09-24 21:09 ` Matthew Wilcox
2018-09-25 0:16 ` Ming Lei
2018-09-25 3:28 ` Matthew Wilcox
2018-09-25 4:10 ` Bart Van Assche
2018-09-25 4:44 ` Matthew Wilcox
2018-09-25 6:55 ` Ming Lei
2018-09-24 15:17 ` Christopher Lameter
2018-09-25 0:20 ` Ming Lei
2018-09-20 14:07 ` Bart Van Assche
2018-09-21 1:56 ` Dave Chinner
2018-09-21 7:08 ` Christoph Hellwig
2018-09-21 7:25 ` Ming Lei
2018-09-21 14:59 ` Jens Axboe
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