Re: [Ksummit-discuss] [CORE TOPIC] Core Kernel support for Compute-Offload Devices

[Jerome Glisse <j.glisse@gmail.com>]

On Mon, Aug 03, 2015 at 10:12:54PM +0100, David Woodhouse wrote:
> On Mon, 2015-08-03 at 23:10 +0200, Joerg Roedel wrote:
> > On Mon, Aug 03, 2015 at 03:01:45PM -0400, Jerome Glisse wrote:
> > > This is not the case with current AMD hw which IIRC only support 8bits or
> > > 9bits for PASID. Dunno if there next hardware will have more bits or not.
> > > So i need to check PCIE spec but i do not think the 20bits is a mandatory
> > > limit.
> > 
> > AMD hardware currently implements PASIDs with 16 bits. Given that only
> > mm_structs which are used by offload devices get one, this should be
> > enough to put them into a global pool and have one PASID per mm_struct.
> 
> I think there are many ARM systems which need this model because of the
> way TLB shootdowns are handled in hardware, and shared with the IOMMU?
> So we have to use the same ASID for both MMU and IOMMU there, AIUI.
> 
> Not that I claim to be an expert on the ARM IOMMUs.
> 

I see that on some platform the ASID <-> page table must be a 1 to 1
relationship. My experience so far on AMD is that it does not and that
while the IOMMU have 16bits their GPU have 9 or 8 bits. Also given that
PASID spec says that device can support different number of bits, it
seems that this gonna end up being a mess with all of specific arch/device
quirks.

Note that i really would like the ASID <-> mm struct 1 to 1 match but
i am just fearing this is not something that can be common to all
platform.

Cheers,
Jérôme