From: Joerg Roedel <joro@8bytes.org>
To: Jerome Glisse <j.glisse@gmail.com>
Cc: Jerome Glisse <jglisse@redhat.com>,
ksummit-discuss@lists.linuxfoundation.org
Subject: Re: [Ksummit-discuss] [CORE TOPIC] Core Kernel support for Compute-Offload Devices
Date: Mon, 3 Aug 2015 23:10:50 +0200 [thread overview]
Message-ID: <20150803211050.GM14980@8bytes.org> (raw)
In-Reply-To: <20150803190145.GC2981@gmail.com>
On Mon, Aug 03, 2015 at 03:01:45PM -0400, Jerome Glisse wrote:
> This is not the case with current AMD hw which IIRC only support 8bits or
> 9bits for PASID. Dunno if there next hardware will have more bits or not.
> So i need to check PCIE spec but i do not think the 20bits is a mandatory
> limit.
AMD hardware currently implements PASIDs with 16 bits. Given that only
mm_structs which are used by offload devices get one, this should be
enough to put them into a global pool and have one PASID per mm_struct.
Joerg
next prev parent reply other threads:[~2015-08-03 21:10 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-30 13:00 Joerg Roedel
2015-07-30 13:31 ` David Woodhouse
2015-07-30 13:54 ` Joerg Roedel
2015-07-31 16:34 ` Jerome Glisse
2015-08-03 18:51 ` David Woodhouse
2015-08-03 19:01 ` Jerome Glisse
2015-08-03 19:07 ` Andy Lutomirski
2015-08-03 19:56 ` Jerome Glisse
2015-08-03 21:10 ` Joerg Roedel [this message]
2015-08-03 21:12 ` David Woodhouse
2015-08-03 21:31 ` Joerg Roedel
2015-08-03 21:34 ` Jerome Glisse
2015-08-03 21:51 ` David Woodhouse
2015-08-04 18:11 ` Catalin Marinas
2015-08-03 22:10 ` Benjamin Herrenschmidt
2015-07-30 22:32 ` Benjamin Herrenschmidt
2015-08-01 16:10 ` Joerg Roedel
2015-07-31 14:52 ` Rik van Riel
2015-07-31 16:13 ` Jerome Glisse
2015-08-01 15:57 ` Joerg Roedel
2015-08-01 19:08 ` Jerome Glisse
2015-08-03 16:02 ` Joerg Roedel
2015-08-03 18:28 ` Jerome Glisse
2015-08-01 20:46 ` Arnd Bergmann
2015-08-03 16:10 ` Joerg Roedel
2015-08-03 19:23 ` Arnd Bergmann
2015-08-04 15:40 ` Christoph Lameter
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