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From: Catalin Marinas <catalin.marinas@arm.com>
To: Andy Lutomirski <luto@amacapital.net>
Cc: "ksummit-discuss@lists.linuxfoundation.org"
	<ksummit-discuss@lists.linuxfoundation.org>
Subject: Re: [Ksummit-discuss] [TECH TOPIC] Semantics of MMIO mapping attributes accross archs
Date: Mon, 6 Jul 2015 10:52:57 +0100	[thread overview]
Message-ID: <20150706095256.GA27723@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CALCETrV82gJKhYbvdrqt3SHE6=42=QBKD8BcQPSukk2nzi1+EA@mail.gmail.com>

On Sun, Jul 05, 2015 at 07:55:39PM +0100, Andy Lutomirski wrote:
> On Sat, Jul 4, 2015 at 8:02 PM, Benjamin Herrenschmidt
> <benh@kernel.crashing.org> wrote:
> > On Sat, 2015-07-04 at 07:12 -0700, Dan Williams wrote:
> >
> >> Another side topic that has come up in this space is the desire to
> >> define a "memremap" api to clean up __iomem abuses for cases where
> >> "memory-like" mappings are needed.
> >>
> >> https://lkml.org/lkml/2015/6/22/100
> >
> > Interesting. I had missed this. There is a similar question about
> > semantics (ordering etc...), ie, are they the same as memory for
> > example ?
> >
> > Another thing we might look into is to what extent should we provide
> > access to the "SAO" mapping attribute that POWER7 and later support
> > (strong ordering, pretty-much x86 like) and whether this can be used
> > on ppc to reduce the need for barriers (that attribute is only available
> > for fully cachable mappings, not generally applicable to IO mappings).
> >
> > That translate to: should your new memremap() take some kinds of flags
> > as an argument ? Though of course providing a cross-arch definition of
> > these flags would be tricky.
> 
> At some point, it would also be nice if the various macros has
> well-defined semantics.  For example, x86 has:
> 
> #define pgprot_noncached(prot)                                          \
>         ((boot_cpu_data.x86 > 3)                                        \
>          ? (__pgprot(pgprot_val(prot) |                                 \
>                      cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS)))     \
>          : (prot))
> 
> Putting aside the pointless boot_cpu_data check (surely the recent PAT
> rework completely obsoletes it), what is
> pgprot_noncached(pgprot_writecombine(x)) supposed to do?  Currently it
> results in garbage.  Should it have well-defined behavior instead?

I never thought composing pgprot_* macros/functions is supposed to
return a combined attribute. On arm32/arm64, this construct is just
returning the outermost prot, i.e. noncached here. Even if we would want
to allow such combination, we don't have enough software PTE bits for
each prot type, so these macros simply generate the corresponding
hardware bits (on newer ARM cores, that's a 3-bit index).

FWIW, on ARM, pgprot_noncached has stronger ordering semantics than what
ioremap_nocache returns and in many (most) cases it's not the
appropriate type for ARM (e.g. video framebuffers should use
writecombine since noncached doesn't even allow unaligned accesses).

-- 
Catalin

  parent reply	other threads:[~2015-07-06  9:53 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-04  8:17 Benjamin Herrenschmidt
2015-07-04 14:12 ` Dan Williams
2015-07-05  3:02   ` Benjamin Herrenschmidt
2015-07-05 18:55     ` Andy Lutomirski
2015-07-05 19:56       ` Benjamin Herrenschmidt
2015-07-05 20:09         ` Andy Lutomirski
2015-07-06  9:33         ` Will Deacon
2015-07-06 22:02           ` Benjamin Herrenschmidt
2015-07-07  9:56             ` Will Deacon
2015-07-07 10:29               ` Will Deacon
2015-07-06  9:52       ` Catalin Marinas [this message]
2015-07-06 17:14         ` Andy Lutomirski
2015-07-06 22:04           ` Benjamin Herrenschmidt
2015-07-06 19:11       ` Luck, Tony
2015-07-07  0:01 ` Luis R. Rodriguez

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