On Mon, 2015-08-03 at 23:10 +0200, Joerg Roedel wrote:
> On Mon, Aug 03, 2015 at 03:01:45PM -0400, Jerome Glisse wrote:
> > This is not the case with current AMD hw which IIRC only support 8bits or
> > 9bits for PASID. Dunno if there next hardware will have more bits or not.
> > So i need to check PCIE spec but i do not think the 20bits is a mandatory
> > limit.
> 
> AMD hardware currently implements PASIDs with 16 bits. Given that only
> mm_structs which are used by offload devices get one, this should be
> enough to put them into a global pool and have one PASID per mm_struct.

I think there are many ARM systems which need this model because of the
way TLB shootdowns are handled in hardware, and shared with the IOMMU?
So we have to use the same ASID for both MMU and IOMMU there, AIUI.

Not that I claim to be an expert on the ARM IOMMUs.

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation