Re: [Ksummit-discuss] [TECH TOPIC] asm-generic implementations of low-level synchronisation constructs

[David Woodhouse <dwmw2@infradead.org>]

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On Thu, 2014-05-08 at 16:27 +0200, Peter Zijlstra wrote:
> 
> So the most common constraint (which you've confirmed is true for ARM as
> well) is that we should not have memory accesses in between an LL/SC.
> 
> Making sure GCC doesn't do any is tricky, the best I can come up with is
> tagging all variables with the register qualifier, like:
> 
> ATOMIC_RET(ptr, __ret, stmt)
> ({
>         register typeof(*ptr) __new, __val;
> 
>         smp_mb__before_llsc();
> 
>         do {
>                 __val = load_locked(ptr);
>                 stmt;
>         } while (!store_conditional(ptr, __new));
> 
>         smp_mb__after_llsc();
> 
>         __ret;
> })
> 
> Now, I'm not at all sure if register still means anything to GCC, but in
> the faint hope that it still sees it as a hint this might just work.

No. Please no. Not even if you sacrifice a goat to the gods of GCC
undefined behaviour.

Acting on condition flags from inline asm is also hard or suboptimal in
some cases too. You're probably better off just having this done in asm
directly.

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse@intel.com                              Intel Corporation

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